The present invention relates to a dynamic random access memory (DRAM), and more particularly, to a technology capable of stabilizing the operation of the DRAM by controlling an enable time of a data input buffer thereof.
In a write operation of a DRAM employing a DDR3 system, a write command is inputted and data inputted through a data input/output (I/O) pin (DQ pin) is inputted into a data input buffer in synchronization with the write command. In this case, the data input buffer is not always in the turn-on state, but is controlled to be turned on/off in order to reduce current consumption.
Generally, the data input buffer is enabled at the time when write command is inputted. However, when the write operation is performed immediately after a read operation, the data input buffer may be turned on for the write operation at the time when data is outputted into the data I/O pin by a read command.
At this time, the data outputted into the data I/O pin may be entered into the data input buffer because the data input buffer is also connected to the data I/O pin. Thus, many blocks included in the data input buffer may be unnecessarily operated. The unnecessary operation of the blocks may cause an increase of the current consumption, and also a resultant noise component may increase the risk of affecting the read operation.
Hereafter, a typical circuit for generating a data input buffer enable signal will be described in detail with reference to FIGS. 1 and 2.
FIG. 1 is a diagram illustrating a typical circuit for generating a data input buffer control signal used in the DDR3 DRAM. The reference symbol “ECASPWT” means an external write command. Since the DDR3 DRAM supports an additive latency, referred to as “AL” hereafter, the circuit includes an AL shifter 10. The AL shifter 10 shifts the write command according to the AL. The AL shifter 10 generates a write command signal CASWT_AL by shifting the write command ECASPWT in response to an internal clock ICLK and a CAS latency CL<5:11>. When the AL=0, the timing of the generation of the write command signal CASWT_AL is identical to that of the input of the write command ECASPWT.
A write signal generating unit 12 receives the internal clock ICLK and a CAS write latency CWL <5:8> and generates write signals EWL_25 and EWL_15 having predetermined timings on the basis of a write latency WL using the write command signal CASWT_AL. In this case, the write signal EWL_25 is generated ahead by 2.5 clocks on the basis of the write latency WL, and the write signal EWL_15 is generated ahead by 1.5 clocks on the basis of the write latency WL.
The write signals EWL_25 and EWL_15 generated in the write signal generating unit 12 are provided to a write maintenance signal generating unit 14 and a control signal generating unit 16. The write maintenance signal generating unit 14 generates a write maintenance signal WTSTBY in synchronization with the internal clock ICLK, which is a signal maintained during a burst length beyond the write latency WL until the write operation is ended. The control signal generating unit 16 generates a data input buffer control signal ENDINDS using the write signals EWL_25 and EWL_15, the write maintenance signal WTSTBY, and a write enable control signal WTS_ALWL.
Here, the write enable control signal WTS_ALWL is generated by a write enable control unit 18 using an external WL pulse EWL_1P and the write command signal CASWT_AL. The external WL pulse EWL_1P is used to maintain the activation state of the write enable control signal WTS_ALWL during WL−1 clocks.
The data input buffer control signal ENDINDS described in FIG. 1 controls the input buffer of the I/O pin (DQ pin) and the I/O strobe pin (DQS pin). Because the DQ pin and DQS pin are commonly used for inputting and outputting data, the output driver and input buffer are commonly connected.
If only the read operation is performed, the input buffer keeps its closed state. Accordingly, there is no problem although data outputted through the pin flows into the input buffer. However, when the write operation is performed after the read operation, that is, the write command following the read command is inputted with a minimum gap as proposed in the spec, the input buffer is enabled while data is outputted, so that the output data may be transferred to the rear end of the input buffer. As a result, there may be blocks unnecessarily operated.
FIG. 2 is a timing diagram illustrating signals used for the circuit in FIG. 1.
The timing diagram of FIG. 2 is based on AL=0, CL=11, and CWL=8, assuming that the write command is inputted with a minimum gap following the read command.
As illustrated in FIG. 2, by the read command, data is outputted through the DQ pin at a time when CL=11. Also, when the write command is inputted, the write enable control signal WTS_ALWL is changed to a logic high level, and maintained until the timing of the WL−1 clocks.
The write signal EWL_25 changes its logic level at the timing of WL−2.5 clocks, and the write signal EWL_15 changes its logic level at the timing of WL−1.5 clocks. Also, in order to maintain a stand-by state until the write operation is completely ended, the write maintenance signal WTSTBY maintains its logic high level from WL−1.5 clocks to WL+3.5 clocks. Finally, by performing a logic OR operation on the four signals, the data input buffer control signal ENDINDS is generated.
According to the operation as described above, while data are outputted through the DQ pin, the data input buffer control signal ENDINDS changes its logic level, so that the input buffer keeps its open state.
Accordingly, in the typical circuit for generating a data input buffer control signal, an operation error may occur due to a conflict of the read data and the write data, and also an excessive current consumption may occur due to unnecessary operation of blocks.